As integrated circuit (IC) features become smaller, process distortions have a growing impact on pattern fidelity in manufacturing and, in turn, on device performance. Examples of process distortions include pattern-dependent line-width biasing, corner rounding, and line end shortening, all of which create patterns on a wafer that are different than patterns defined on a corresponding mask or reticle.
In recent years, optical process correction (OPC) techniques have been developed that compensate for distortions that occur in printing. Originally, OPC modifications could be a simple set of rules applied to bias or otherwise alter a layout. However, as patterns became more intricate and distortions more severe, model-based OPC techniques were developed.
In model-based OPC, a process model is developed to allow simulation of the processing effects, typically through making a set of convolution kernels. Such kernels are usually chosen to be an orthogonal set, with the relative magnitudes determined by a calibration procedure with empirically gathered data from the distorting process. The simulation consists of calculating a mathematical convolution of the layout pattern with the kernels. If the simulated image is significantly different from the target layer (i.e., original layout), edges corresponding to the out-of-spec patterns are moved and a new layout is generated. The new layout is then used as an input to the simulator to estimate how the revised layout will print. Once an image is formed with specified tolerances, OPC correction is achieved and the final layout is passed on to be fabricated as a mask or reticle. The mathematically based techniques for analyzing image distortions can also be applied to resist processing distortions.
Another processing distortion that affects a wafer is the etch effect, whereby the patterns that are etched on the surface of a wafer differ from a desired pattern. In principle, etched distortions could be corrected using the iterative techniques applied to imaging and resist distortions. However, in practice the results are often inaccurate. This is because the physical phenomena of etching, such as density-based microloading and certain etch shadowing effects are non-linear and not well described by the linear mathematics of convolution. Furthermore, most optical and resist effects occur over a relatively small distance, typically on the order of 1-1.5 microns. Etch effects are dictated by the physical properties of a plasma that is formed above the wafer and often have interaction diameters of 4-5 microns. Since the computation time of convolution increases with the area, an increase in diameter from 1 to 5 microns would increase the area and the associated computation time by a factor of 25. Alternatively, attempts have been made to add separate etch simulators as part of an OPC correction loop. However, etch simulators tend to be computationally intensive and the addition of an etch simulator within each pass of an OPC loop can make the OPC correction process impractical to implement.
Given these problems, there is a need for a method of correcting layout data for etch distortions in a manner that is not computationally impractical yet still produces accurate results.